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    说明:Microchip's LAN9513/LAN9513i are the industry's first fully-integrated, Hi-Speed USB 2.0 hub and high-performance 10/100 Ethernet controllers. The LAN9513/LAN9513i are specifically designed to provide system architects with a low-cost, power-efficient, small-footprint USB to Ethernet and multi-port USB connectivity solution in a single package.The LAN9513/LAN9513i contain a Hi-Speed USB 2.0 hub with three fully-integrated downstream USB 2.0 PHYs, an integrated upstream USB 2.0 PHY, a 10/100 Ethernet MAC/PHY

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    ¥67.512000

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    说明:The LAN9312 is a full featured, 2 port 10/100 managed Ethernet switch designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9312 combines all the functions of a 10/100 switch system, including the switch fabric, packet buffers, buffer manager, media access controllers (MACs), PHY transceivers, and host bus interface. The LAN9312 complies with the IEEE 802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol specification

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    ¥85.796500

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    说明:The LAN91C110 is designed to facilitate the implementation of second generation Fast Ethernet PC Card adapters and other non-PCI connectivity products. The LAN91C110 is a digital device that implements the Media Access Control (MAC) portion of the CSMA/CD protocol at 10 and 100 Mbps, and couples it with a lean and fast data and control path system architecture to ensure that the CPU to packet RAM data movement does not cause a bottleneck at 100 Mbps.The LAN91C110 implements a generic 16-bit host interface w

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    ¥96.049400

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    说明:The KSZ8765 is a highly integrated, Layer 2-managed, five-port switch with numerous features designed to reduce overall system cost. It is intended for cost-sensitive applications requiring four 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port.The KSZ8765CLX incorporates a small package outline, low power consumption with internal biasing, and on-chip termination. Its extensive set of features include enhanced power management, programmable rate limiting and priority ratio, tagged and por

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    说明:The KSZ8051 is an AEC-Q100 standard qualified single-supply 10Base-T/100Base-TX Ethernet physical-layer transceiver for automotive applications.The KSZ8051 is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core. The KSZ8051MNLU/V offers the Media Independent Interface(MII) and the KSZ8051RNLUB-VAO offers the Reduced Media Independent Interface(RMI

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    说明:The LAN9218(i) is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9218(i) has been specifically architected to provide the highest performance possible for any given architecture. The LAN9218(i) is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX.The LAN9218(i) includes an integrated Ethernet MAC and PHY with a high-performance SRAM-l

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    说明:The KSZ8842-series of 2-port switches includes PCI and non-PCI CPU interfaces.The datasheet describes the KSZ8842-PMQL/PMBL PCI CPU interface chips. KSZ8842-PMQL is PQFP package chip, KSZ8842-PMBL is LFBGA package chip. For information on the KSZ8842-MQL/MBL CPU non-PCI interface switches, refer to the KSZ8842-MQL/MBL datasheet.The KSZ8842-PMQL/PMBL is the industry's first fully managed 2-port switch with a 32-bit/33MHz PCI processor interface. It is a proven, 4th generation, integrated Layer 2 switch that

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    说明:The KSZ9893 is a fully integrated layer 2, managed, three-port gigabit Ethernet switch with numerous advanced features. Two of the three ports incorporate 10/100/1000 Mbps PHYs. The other port has interfaces that can be configured as RGMII, MII or RMII. This port may connect directly to a host processor or to an external PHY.Full register access is available by SPI or I2C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface.Securi

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