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    说明:Microchip's LAN8740A/LAN8740Ai?are the latest generation of low-power, 10/100 Fast Ethernet PHYs featuring Energy Efficient Ethernet (IEEE 802.3az) and Wake-On-LAN functionality, which provide system sleep modes for improved power savings. The LAN8740A/LAN8740Ai feature deterministic loop back delay, assuring real-time system performance as well as cable diagnostics which reduce network installation costs. These devices?are available in both commercial (0° to 70°C) and industrial (-40° to 85°C) temperature

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    ¥9.302300

    ¥9.137400

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    说明:The KSZ8001 is a 10BASE-T/100BASE-TX/100BASE-FX Physical Layer Transceiver, powered by a single 3.3v supply. With core operation at 1.8 volts the device is low power, consuming typically 172mW.The solution provides MII/RMII/SMII host interfaces commonly available on Microcontrollers, Microprocessors or FPGA's with integrated IEEE 802.3 MACs. A unique mixed-signal design extends signaling distance while reducing power consumption. HP Auto MDI/MDI-X provides the most robust solution for eliminating the need

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    说明:Microchip's LAN7500 is a Hi-Speed USB 2.0 to 10/100/1000 Gigabit Ethernet controller providing a high-performance and cost-effective USB to Ethernet connectivity solution. The LAN7500 contains an integrated 10/100/1000 Gigabit Ethernet PHY, USB PHY, Hi-Speed USB 2.0 device controller, 10/100/1000 Gigabit Ethernet MAC, TAP controller, EEPROM controller and a FIFO controller with a total of 32KB internal packet buffering. The device supports 10BASE-T,100BASE-TXand 1000BASE-T Ethernet and implements Control, I

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    ¥45.599700

    ¥17.654000

    ¥17.033200

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    说明:The LAN9250 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance,flexibility, ease of integration and system cost control are required. The LAN9250 has been specifically designed to provide high performance and throughput for 16-bit applications. The LAN9250 complies with the IEEE802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol, IEEE 802.3az Energy Efficient Ethernet (EEE)(100Mbps only), and the IEEE 1588v2 precision time protocol.

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    ¥54.387900

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    ¥34.706600

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    说明:The Microchip LAN8672 is a compact, low power, and cost-effective single-port 10BASE-T1S Ethernet physical layer transceiver designed according to the IEEE Std 802.3cg-2019TMspecification. The device provides 10 Mbit/s half-duplex transmit and receive capability over single-balanced pair medium such as Unshielded Twisted Pair (UTP) cable. The LAN8672 is designed for use in applications requiring extended temperature range (-40°C to +125°C). The device is also compliant to industrial EMC and EMI requirements

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    说明:The KSZ8765 is a highly integrated, Layer 2-managed, five-port switch with numerous features designed to reduce overall system cost. It is intended for cost-sensitive applications requiring four 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port.The KSZ8765CLX incorporates a small package outline, low power consumption with internal biasing, and on-chip termination. Its extensive set of features include enhanced power management, programmable rate limiting and priority ratio, tagged and por

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    说明:The KSZ8842-series of 2-port switches includes PCI and non-PCI CPU interfaces.The datasheet describes the KSZ8842-PMQL/PMBL PCI CPU interface chips. KSZ8842-PMQL is PQFP package chip, KSZ8842-PMBL is LFBGA package chip. For information on the KSZ8842-MQL/MBL CPU non-PCI interface switches, refer to the KSZ8842-MQL/MBL datasheet.The KSZ8842-PMQL/PMBL is the industry's first fully managed 2-port switch with a 32-bit/33MHz PCI processor interface. It is a proven, 4th generation, integrated Layer 2 switch that

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    ¥130.086700

    ¥50.343000

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    说明:The Microchip LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111 is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32-bit, 16-bit or 8-bit bus Host interface in

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    ¥326.259500

    ¥126.255200

    ¥121.822300

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    ¥517.174900

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